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Springer - High performance Packet Switching Architectures(2007)List of Contributors ..............................................................................................xi1 Architectures of Internet Switches and Routers ............................................ 1Xin Li, Lotfi Mhamdi, Jing Liu, Konghong Pun, and Mounir Hamdi1.1 Introduction ...............................................................................................21.2 Bufferless Crossbar Switches ................................................................... 31.2.1 Introduction to Switch Fabrics ....................................................... 31.2.2 Output-queued Switches ................................................................41.2.3 Input-queued Switches ..................................................................41.2.4 Scheduling Algorithms for VOQ Switches ................................... 51.2.5 Combined Input–Ouput-queued Switches ..................................... 91.3 Buffered Crossbar Switches .................................................................... 121.3.1 Buffered Crossbar Switches Overview......................................... 121.3.2 The VOQ/BCS Architecture ........................................................131.4 Multi-stage Switching ............................................................................. 191.4.1 Architecture Choice......................................................................191.4.2 The MSM Clos-network Architecture ......................................... 201.4.3 The Bufferless Clos-network Architecture ................................... 231.5 Optical Packet Switching ........................................................................271.5.1 Multi-rack Hybrid Opto-electronic Switch Architecture ............. 271.5.2 Optical Fabrics .............................................................................281.5.3 Reduced Rate Scheduling ............................................................301.5.4 Time Slot Assignment Approach ................................................. 301.5.5 DOUBLE Algorithm ...................................................................321.5.6 ADJUST Algorithm .....................................................................321.6 Conclusion ....... .......................................................................................342 Theoretical Performance of Input-queued SwitchesUsing Lyapunov Methodology....................................................................... 39Andrea Bianco, Paolo Giaccone, Emilio Leonardi, Marco Mellia,and Fabio Neri2.1 Introduction .............................................................................................392.2 Theoretical Framework ...........................................................................41v iii Contents2.2.1 Description of the Queueing System ........................................... 412.2.2 Stability Definitions for a Queueing System ............................... 432.2.3 Lyapunov Methodology ..............................................................442.2.4 Lyapunov Methodology to Bound Queue Sizes and Delays ....... 472.2.5 Application to a Single Queue ..................................................... 482.2.6 Final Remarks ..............................................................................492.3 Performance of a Single Switch .............................................................. 502.3.1 Stability Region of Pure Input-queued Switches ......................... 512.3.2 Delay Bounds for Maximal Weight Matching ............................. 542.3.3 Stability Region of CIOQ with Speedup 2 ................................... 552.3.4 Scheduling Variable-size Packets................................................. 572.4 Networks of IQ Switches......................................................................... 582.4.1 Theoretical Performance...............................................................592.5 Conclusions .............................................................................................613 Adaptive Batched Scheduling for Packet Switching with Delays ............... 65Kevin Ross and Nicholas Bambos3.1 Introduction .............................................................................................653.2 Switching Modes with Delays: A General Model ................................... 663.3 Batch Scheduling Algorithms ................................................................. 693.3.1 Fixed Batch Policies .....................................................................703.3.2 Adaptive Batch Policies................................................................ 723.3.3 The Simple-batch Static Schedule ................................................ 733.4 An Interesting Application: Optical Networks ........................................ 743.5 Throughput Maximization via Adaptive Batch Schedules ...................... 763.6 Summary .................................................................................................784 Geometry of Packet Switching: Maximal Throughput ConeScheduling Algorithms .................................................................................. 81Kevin Ross and Nicholas Bambos4.1 Introduction .............................................................................................814.2 Backlog Dynamics of Packet Switches.................................................... 844.3 Switch Throughput and Rate Stability ..................................................... 864.4 Cone Algorithms for Packet Scheduling.................................................. 884.4.1 Projective Cone Scheduling (PCS)............................................... 894.4.2 Relaxation, Generalizations, and Delayed PCS (D-PCS)............. 904.4.3 Argument Why PCS and D-PCS Maximize Throughput ............. 924.4.4 Quality of Service and Load Balancing........................................ 934.5 Complexity in Cone Schedules – Scalable PCS Algorithms ................... 954.5.1 Approximate PCS......................................................................... 954.5.2 Local PCS..................................................................................... 954.6 Final Remarks .........................................................................................985 Fabric on a Chip: A Memory-management Perspective ........................... 101Itamar Elhanany, Vahid Tabatabaee, and Brad Matthews5.1 Introduction ...........................................................................................1015.1.1 Benefits of the Fabric-on-a-Chip Approach ............................... 1025.2 Emulating an Output-queued Switch .................................................... 103Contents ix5.3 Packet Placement Algorithm ................................................................. 1055.3.1 Switch Architecture ................................................................... 1055.3.2 Memory-management Algorithm and Related Resourses .......... 1065.3.3 Sufficiency Condition on the Number of Memories................... 1095.4 Implementation Considerations ............................................................. 1145.4.1 Logic Dataflow........................................................................... 1145.4.2 FPGA Implementation Results ................................................... 1195.5 Conclusions ........................................................................................... 1206 Packet Switch with Internally Buffered Crossbars.................................... 121Zhen Guo, Roberto Rojas-Cessa, and Nirwan Ansari6.1 Introduction to Packet Switches.............................................................1216.2 Crossbar-based Switches .......................................................................1226.3 Internally Buffered Crossbars ................................................................ 1246.4 Combined Input–Crosspoint Buffered (CICB) Crossbars ..................... 1266.4.1 FIFO–CICO Switches ................................................................ 1266.4.2 VOQ–CICB Switches ................................................................ 1286.4.3 Separating Matching into Input and Output Arbitrations ........... 1306.4.4 Weighted Arbitration Schemes................................................... 1306.4.5 Arbitration Schemes based on Round-robin Selection .............. 1356.5 CICB Switches with Internal Variable-length Packets .......................... 1416.6 Output Emulation by CICB Switches ................................................... 1416.7 Conclusions ........................................................................................... 1447 Dual Scheduling Algorithm in a Generalized Switch:Asymptotic Optimality and Throughput Optimality................................. 147Lijun Chen, Steven H. Low, and John C. Doyle7.1 Introduction ...........................................................................................1487.2 System Model .. .....................................................................................1507.2.1 Queue Length Dynamics ........................................................... 1517.2.2 Dual Scheduling Algorithm ....................................................... 1527.3 Asymptotic Optimality and Fairness ..................................................... 1537.3.1 An Ideal Reference System ....................................................... 1537.3.2 Stochastic Stability .................................................................... 1547.3.3 Asymptotic Optimality and Fairness .......................................... 1557.4 Throughput-optimal Scheduling ...........................................................1597.4.1 Throughput Optimality and Fairness ......................................... 1597.4.2 Optimality Proof ........................................................................1607.4.3 Flows with Exponentially Distributed Size ............................... 1637.5 A New Scheduling Architecture ........................................................... 1657.6 Conclusions ........................................................................................... 1668 The Combined Input and Crosspoint Queued Switch............................... 169Kenji Yoshigoe and Ken Christensen8.1 Introduction ...........................................................................................1698.2 History of the CICQ Switch .................................................................. 1728.3 Performance of CICQ Cell Switching .................................................. 1758.3.1 Traffic Models ........................................................................... 176x Contents8.3.2 Simulation Experiments .............................................................1778.4 Performance of CICQ Packet Switching .............................................. 1798.4.1 Traffic Models ........................................................................... 1798.4.2 Simulation Experiments .............................................................1798.5 Design of Fast Round-robin Arbiters .................................................... 1818.5.1 Existing RR Arbiter Designs ..................................................... 1828.5.2 A New Short-term Fair RR Arbiter – The Masked PriorityEncoder (MPE) ...... .................................................................... 1838.5.3 A New Fast Long-term Fair RR Arbiter – The Overlapped RR(ORR) Arbiter ............................................................................. 1868.6 Future Directions – The CICQ with VCQ ............................................ 1888.6.1 Design of Virtual Crosspoint Queueing (VCQ) ........................ 1898.6.2 Evaluation of CICQ Cell Switch with VCQ .............................. 1908.7 Summary ...............................................................................................1929 Time–Space Label Switching Protocol (TSL-SP)....................................... 197Anpeng Huang, Biswanath Mukherjee, Linzhen Xie, and Zhengbin Li9.1 Introduction ...........................................................................................1979.2 Time Label ............................................................................................ 1989.3 Space Label ........................................................................................... 2009.4 Time–Space Label Switching Protocol (TSL-SP) ................................. 2019.5 Illustrative Results .................................................................................2059.6 Summary ...............................................................................................20910 Hybrid Open Hash Tables for Network Processors................................... 211Dale Parson, Qing Ye, and Liang Cheng10.1 Introduction ........................................................................................... 21110.2 Conventional Hash Algorithms ............................................................. 21310.2.1 Chained Hash Tables ................................................................ 21410.2.2 Open Hash Tables ..................................................................... 21510.3 Performance Degradation Problem ...................................................... 21610.3.1 Improvements .......................................................................... 21810.4 Hybrid Open Hash Tables .................................................................... 21910.4.1 Basic Operations ...................................................................... 21910.4.2 Basic Ideas ............................................................................... 21910.4.3 Performance Evaluation ......................................................... 22010.5 Hybrid Open Hash Table Enhancement ............................................... 22210.5.1 Flaws of Hybrid Open Hash Table ........................................... 22210.5.2 Dynamic Enhancement .............................................................22310.5.3 Adaptative Enhancement .......................................................... 22410.5.4 Timeout Enhancement .............................................................. 22410.5.5 Performance Evaluation ......................................................... 22410.6 Extended Discussions of Concurrency Issues ...................................... 22510.6.1 Insertion ....................................................................................22510.6.2 Clean-to-copy Phase Change .................................................... 22610.6.2 Timestamps................................................................................22710.7 Conclusion ....... ..................................................................................... 227Index .................................... ............................................................................... 229


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