下载地址：
下载地址1（本站为飞网专业下载站，域名：down.cfei.net）
资源简介：
spdif，aes3接口This module is an example of a clock divider to generate the three clockenables required by the AES3 Tx module. When provided with a 24.576 MHz clockinput, this module can produce clock enables for sample rates based around48 kHz, up to 192 kHz. When provided with a 22.5792 MHz clock, this module can produce clock enables for sample rates based around the 44.1 kHz, up to 176.4 kHz.
飞网下载站，免费下载共享资料，内容涉及教育资源、专业资料、IT资源、娱乐生活、经济管理、办公文书、游戏资料等。
