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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity scan_led is port( clk:in std_logic; sg:out std_logic_vector(6 downto 0); bt:out std_logic_vector(7 downto 0)); end;architecture one of scan_led is signal cnt8:std_logic_vector(2 downto 0); signal a:integer range 0 to 15;beginp1:process(cnt8)begin case cnt8 is when "000"=>bt<="00000001";a<=1; when "001"=>bt<="00000010";a<=3; when "010"=>bt<="00000100";a<=5; when "011"=>bt<="00001000";
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